A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance, C=.epsilon.A/d, where .epsilon. is the dielectric constant of the capacitor dielectric, A is the electrode (or storage node) area and d is the interelectrode spacing. The conditions of DRAM operation such as operating voltage, leakage rate and refresh rate, will in general mandate that a certain minimum charge be stored by the capacitor.
In the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. For example, the area allowed for a single cell in a 64-Mbit DRAM is only about 1.4 .mu.m.sup.2. In such limited areas, it is difficult to provide sufficient capacitance using conventional stacked capacitor structures. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include new structures utilizing trench and stacked capacitors, as well as utilizing new capacitor dielectric materials having higher dielectric constants.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant. However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area.
To maintain high cell capacitance in the face of small lateral cell dimensions, one technique has been to utilize so-called "textured" electrodes. A textured electrode typically comprises a polysilicon (poly) or other conductive material having an irregular or rough surface morphology. The textured surface morphology increases considerably the electrode surface area, thus increasing capacitance. For example, a typical prior art texturizing process may increase electrode area by about 2.5 times, while maintaining the same lateral profile.
A textured electrode in a cell capacitor may be processed in several ways to produce an increased surface area with respect to the available lateral dimension. For example, patterned poly or a-Si is subjected to a seeding process, whereby a desired density of incubation sites are generated. Subsequently, the seeded electrodes are annealed at temperatures which induce atomic surface migration of silicon. The incubation sites present a significantly lower local diffusivity of silicon atoms, causing local accumulation of material. The result is a textured electrode, often having a hemispherically grained morphology (Hemispherically Grained Silicon or HSG), with enhanced surface area. Such techniques are shown by way of example in T. Mine et al., "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs", Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, pp. 137-140, 1989; H. Watanabe et al., "A New Stacked Capacitor Structure Using Hemispherical-Grain (HSG) Poly-Silicon Electrodes", Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, Sendai, pp. 873-876, 1990, Hayashide et al., "Fabrication of Storage Capacitance-Enhanced Capacitors with a rough Electrode", Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, Sendai, pp. 869-872; Fazan et al., "Thin Nitride Films on Textured Polysilicon to Increase Multimegabit DRAM Cell Charge Capacity", IEEE Electron Device Letters, Vol. 11, No. 7, Jul. 7, 1990; Fazan et al., "Electrical Characterization of Textured Interpoly Capacitors For Advanced Stacked DRAMs"; and M. Yoshimaru et al., "Rugged Surface Poly-Si Electrode and Low Temperature Deposited Si3N4 for 64 Mb and Beyond STC DRAM Cell", Oki Electric Industry Co., Ltd., VLSI R&D Laboratory 550-1, Higashiasakawa, Hachioji, Tokyo 193, Japan.
While texturizing capacitor electrodes is advantageous from the perspective of increasing capacitance, the textured electrodes themselves present a problem when forming a thin (.apprxeq.5-10 nm) conformal overlayer such as a dielectric film to serve as the interelectrode capacitor dielectric. A common problem associated with all of the aforementioned textured capacitor structures is depositing a sufficiently thin, conformal and uniform dielectric over the textured cell plates. Nonuniformities in ultra thin film dielectrics contribute to enhanced leakage current and premature dielectric breakdown. Moreover, maintaining good dielectric breakdown characteristics between the electrodes in increasingly smaller STC capacitors becomes a major concern when insulator thickness is appropriately scaled. Thus, there is increasing need in the industry for deposition processes capable of providing uniform ultrathin films overlaying textured surfaces.